Texas Instruments TMS320DM644x - Manual (Page 31)

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Registers
Figure 27. GPIO Bank 4 Set Falling Edge Interrupt Register (SET_FAL_TRIG4)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved SETFAL70 SETFAL69 SETFAL68 SETFAL67 SETFAL66 SETFAL65 SETFAL64
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIGn) Field Descriptions
Bit Field Value Description
31-16 SETFALn Enable falling edge interrupt detection on GPIO pin n. Reading the SETFALn bit returns the state of
pin n on GPIO bank 2I + 1. This bit field configures the GPIO pins on GPIO banks 1 and 3.
0 No effect.
1 Interrupt is caused by a high-to-low transition on GPIO pin n.
15-0 SETFALn Enable falling edge interrupt detection on GPIO pin n. Reading the SETFALn bit returns the state of
pin n on GPIO bank 2I. This bit field configures the GPIO pins on GPIO banks 0, 2, and 4.
0 No effect.
1 Interrupt is caused by a high-to-low transition on GPIO pin n.
SPRUE25 – December 2005 General-Purpose Input/Output (GPIO) 31