Texas Instruments TMS320DM644x - Manual (Page 33)

www.ti.com
Registers
Figure 30. GPIO Bank 4 Clear Falling Edge Interrupt Register (CLR_FAL_TRIG4)
31 16
Reserved
R-0
15 8
Reserved
R-0
7 6 5 4 3 2 1 0
Reserved CLRFAL70 CLRFAL69 CLRFAL68 CLRFAL67 CLRFAL66 CLRFAL65 CLRFAL64
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions
Bit Field Value Description
31-16 CLRFALn Disable falling edge interrupt detection on GPIO pin n. Reading the CLRFALn bit returns the
complement state of pin n on GPIO bank 2I + 1. This bit field configures the GPIO pins on GPIO
banks 1 and 3.
0 No effect.
1 No interrupt is caused by a high-to-low transition on GPIO pin n.
15-0 CLRFALn Disable falling edge interrupt detection on GPIO pin n. Reading the CLRFALn bit returns the
complement state of pin n on GPIO bank 2I. This bit field configures the GPIO pins on GPIO banks
0, 2, and 4.
0 No effect.
1 No interrupt is caused by a high-to-low transition on GPIO pin n.
SPRUE25 – December 2005 General-Purpose Input/Output (GPIO) 33