Texas Instruments TMS320DM644x - Manual (Page 28)

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3.9 GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn)
Registers
The GPIO clear rising edge interrupt register (CLR_RIS_TRIGn) disables a rising edge on the GPIO pin
from generating a GPIO interrupt. The GPIO clear rising edge interrupt register (CLR_RIS_TRIG01) is
shown in
Figure 22 , CLR_RIS_TRIG23 is shown in Figure 23 , CLR_RIS_TRIG4 is shown in Figure 24 ,
and described in Table 13 . See Table 1 to determine the CLR_RIS_TRIGn bit associated with each GPIO
bank and pin number.
Figure 22. GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG01)
31 30 29 28 27 26 25 24
CLRRIS31 CLRRIS30 CLRRIS29 CLRRIS28 CLRRIS27 CLRRIS26 CLRRIS25 CLRRIS24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
CLRRIS23 CLRRIS22 CLRRIS21 CLRRIS20 CLRRIS19 CLRRIS18 CLRRIS17 CLRRIS16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
CLRRIS15 CLRRIS14 CLRRIS13 CLRRIS12 CLRRIS11 CLRRIS10 CLRRIS9 CLRRIS8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
CLRRIS7 CLRRIS6 CLRRIS5 CLRRIS4 CLRRIS3 CLRRIS2 CLRRIS1 CLRRIS0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 23. GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register (CLR_RIS_TRIG23)
31 30 29 28 27 26 25 24
CLRRIS63 CLRRIS62 CLRRIS61 CLRRIS60 CLRRIS59 CLRRIS58 CLRRIS57 CLRRIS56
R/W-10 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
CLRRIS55 CLRRIS54 CLRRIS53 CLRRIS52 CLRRIS51 CLRRIS50 CLRRIS49 CLRRIS48
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
CLRRIS47 CLRRIS46 CLRRIS45 CLRRIS44 CLRRIS43 CLRRIS42 CLRRIS41 CLRRIS40
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
CLRRIS39 CLRRIS38 CLRRIS37 CLRRIS36 CLRRIS35 CLRRIS34 CLRRIS33 CLRRIS32
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
28 General-Purpose Input/Output (GPIO) SPRUE25 – December 2005