6 gpio clear data register (clr_datan), Clr_data4), Section 3.6 – Texas Instruments TMS320DM644x User Manual
Page 23
www.ti.com
3.6
GPIO Clear Data Register (CLR_DATAn)
Registers
The GPIO clear data register (CLR_DATAn) controls driving low the corresponding GPIO pin n in GPIO
bank I, if the pin is configured as an output (DIRn = 0). Writes do not affect pins not configured as GPIO
outputs. The bits in CLR_DATAn are set or cleared by writing directly to this register. A read of the CLRn
bit returns the output drive state of the corresponding GPIO pin n. The GPIO clear data register
(CLR_DATA01) is shown in
, CLR_DATA23 is shown in
, CLR_DATA4 is shown in
, and described in
. See
to determine the CLR_DATAn bit associated with each
GPIO bank and pin number.
Figure 13. GPIO Banks 0 and 1 Clear Data Register (CLR_DATA01)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLR31 CLR30 CLR29 CLR28 CLR27 CLR26 CLR25 CLR24 CLR23 CLR22 CLR21 CLR20 CLR19 CLR18 CLR17 CLR16
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR15 CLR14 CLR13 CLR12 CLR11 CLR10
CLR9
CLR8
CLR7
CLR6
CLR5
CLR4
CLR3
CLR2
CLR1
CLR0
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 14. GPIO Banks 2 and 3 Clear Data Register (CLR_DATA23)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CLR63 CLR62 CLR61 CLR60 CLR59 CLR58 CLR57 CLR56 CLR55 CLR54 CLR53 CLR52 CLR51 CLR50 CLR49 CLR48
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLR47 CLR46 CLR45 CLR44 CLR43 CLR42 CLR41 CLR40 CLR39 CLR38 CLR37 CLR36 CLR35 CLR34 CLR33 CLR32
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 15. GPIO Bank 4 Clear Data Register (CLR_DATA4)
31
16
Reserved
R-0
15
7
6
5
4
3
2
1
0
Reserved
CLR70 CLR69 CLR68 CLR67 CLR66 CLR65 CLR64
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUE25 – December 2005
General-Purpose Input/Output (GPIO)
23