Texas Instruments TMS320DM644x - Manual (Page 26)

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3.8 GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIGn)
Registers
The GPIO set rising edge interrupt register (SET_RIS_TRIGn) enables a rising edge on the GPIO pin to
generate a GPIO interrupt. The GPIO set rising edge interrupt register (SET_RIS_TRIG01) is shown in
Figure 19 , SET_RIS_TRIG23 is shown in Figure 20 , SET_RIS_TRIG4 is shown in Figure 21 , and
described in Table 12 . See Table 1 to determine the SET_RIS_TRIGn bit associated with each GPIO
bank and pin number.
Figure 19. GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (SET_RIS_TRIG01)
31 30 29 28 27 26 25 24
SETRIS31 SETRIS30 SETRIS29 SETRIS28 SETRIS27 SETRIS26 SETRIS25 SETRIS24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
SETRIS23 SETRIS22 SETRIS21 SETRIS20 SETRIS19 SETRIS18 SETRIS17 SETRIS16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
SETRIS15 SETRIS14 SETRIS13 SETRIS12 SETRIS11 SETRIS10 SETRIS9 SETRIS8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
SETRIS7 SETRIS6 SETRIS5 SETRIS4 SETRIS3 SETRIS2 SETRIS1 SETRIS0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Figure 20. GPIO Banks 2 and 3 Set Rising Edge Interrupt Register (SET_RIS_TRIG23)
31 30 29 28 27 26 25 24
SETRIS63 SETRIS62 SETRIS61 SETRIS60 SETRIS59 SETRIS58 SETRIS57 SETRIS56
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
SETRIS55 SETRIS54 SETRIS53 SETRIS52 SETRIS51 SETRIS50 SETRIS49 SETRIS48
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
SETRIS47 SETRIS46 SETRIS45 SETRIS44 SETRIS43 SETRIS42 SETRIS41 SETRIS40
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
SETRIS39 SETRIS38 SETRIS37 SETRIS36 SETRIS35 SETRIS34 SETRIS33 SETRIS32
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
26 General-Purpose Input/Output (GPIO) SPRUE25 – December 2005