Texas Instruments TMS320DM644x - Manual (Page 24)

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Registers
Table 10. GPIO Clear Data Register (CLR_DATAn) Field Descriptions
Bit Field Value Description
31-16 CLRn Clear output drive state of GPIO pin n. The CLRn bit is used to clear the output of pin n on GPIO bank
2/ + 1 only when pin n is configured as an output (DIRn = 0). The CLRn bit is ignored when GPIO pin n is
configured as an input. Writing a 1 to the CLRn bit clears the output drive state of the corresponding GPIO
pin n; reading the CLRn bit returns the output drive state of the corresponding GPIO pin n. This bit field
configures the GPIO pins on GPIO banks 1 and 3.
0 No effect.
1 Clear GPIO pin n output to 0.
15-0 CLRn Clear output drive state of GPIO pin n. The CLRn bit is used to clear the output of pin n on GPIO bank 2I
only when pin n is configured as an output (DIRn = 0). The CLRn bit is ignored when GPIO pin n is
configured as an input. Writing a 1 to the CLRn bit clears the output drive state of the corresponding GPIO
pin n; reading the CLRn bit returns the output drive state of the corresponding GPIO pin n. This bit field
configures the GPIO pins on GPIO banks 0, 2, and 4.
0 No effect.
1 Clear GPIO pin n output to 0.
General-Purpose Input/Output (GPIO) 24 SPRUE25 – December 2005