National Instruments PXI NI 5401 - Manual (Page 7)

Contents
© National Instruments Corporation vii NI 5401 User Manual
Figure 2-1. NI 5401 Block Diagram ........................................................................2-1
Figure 2-2. Waveform Data Path Block Diagram....................................................2-2
Figure 2-3. DDS Building Blocks ............................................................................2-3
Figure 2-4. Waveform Generation Trigger Sources ................................................2-5
Figure 2-5. Single Trigger Mode .............................................................................2-6
Figure 2-6. Continuous Trigger Mode .....................................................................2-6
Figure 2-7. Stepped Trigger Mode...........................................................................2-7
Figure 2-8. Analog Output and SYNC Out Block Diagram ....................................2-8
Figure 2-9. Waveform and Trigger Timings............................................................2-8
Figure 2-10. Output Attenuation Chain .....................................................................2-9
Figure 2-11. PLL Architecture for the NI 5401 for PCI ............................................2-12
Figure 2-12. PLL Architecture for the NI 5401 for PXI ............................................2-12
Figure 2-13. Analog Filter Correction .......................................................................2-13
Figure 2-14. RTSI Trigger Lines and Routing for the NI 5401 for PCI ....................2-14
Figure 2-15. PXI Trigger Lines, 10 MHz Backplane Oscillator, and
Routing for the NI 5401 for PXI ...........................................................2-14
Table
Table 1-1. Digital Connector Signal Descriptions..................................................1-6