National Instruments PXI NI 5401 User Manual
Page 58
Index
I-2
www.natinst.com
phase-locked loops and board
synchronization, 2-11 to 2-12
RTSI/PXI trigger lines, 2-14 to 2-15
triggering, 2-4 to 2-7
continuous trigger mode, 2-6
single trigger mode, 2-5 to 2-6
stepped trigger mode, 2-7
trigger sources, 2-4 to 2-5
waveform generation, 2-2
I
impedance, output, 2-10
instruction FIFO, 2-3
internal clock specifications, A-4
I/O connectors, 1-2 to 1-7
ARB connector, 1-3
I/O connectors on front panel (figure), 1-2
Pattern Out connector, 1-5 to 1-6
pin assignments (figure), 1-5
signal descriptions (table), 1-6
PLL Ref connector, 1-4
SHC50-68 50-pin cable connector,
1-6 to 1-7
pin assignments (figure), 1-7
signals, 1-6
SYNC connector, 1-3 to 1-4
I/O connectors (figure), 1-2
L
LabVIEW and LabWindows/CVI software,
1-9 to 1-10
lookup memory
description, 2-3
frequency resolution and lookup memory,
C-1 to C-2
lookup waveform memory, 2-3
M
mechanical specifications, A-4
multiple frequencies, generating in sequence,
1-13 to 1-14
N
National Instruments Web support, D-1 to D-2
NI 5401. See also function generator
operation.
block diagram, 2-1
components, 2-2
connecting signals, 1-2 to 1-7
ARB connector, 1-3
I/O connectors (figure), 1-2
Pattern Out connector, 1-5 to 1-6
PLL Ref connector, 1-4
SHC50-68 50-pin cable connector,
1-6 to 1-7
SYNC connector, 1-3 to 1-4
features, 1-1
PLL architecture (figures), 2-12
power-up and reset conditions, 1-16
software options, 1-8 to 1-10
NI-FGEN instrument driver, 1-9
O
online problem-solving and diagnostic
resources, D-1
operational mode specifications, A-3
optional accessories, B-1
output attenuation, 2-9 to 2-11
P
Pattern Out connector, 1-5 to 1-6
pin assignments (figure), 1-5
signal descriptions (table), 1-6
phase-locked loop (PLL) Ref connector, 1-4