Interrupts, Disable 1: enable, No interrupt requested 1: interrupt requested – Lucent Technologies MN10285K User Manual
Page 65: Interrupt undetected 1: interrupt detected, Sets the priority from 0 to 6, Adm0ie: address match 0 interrupt enable flag, Anir: a/d conversion end interrupt request flag, Anid: a/d conversion end interrupt detect flag, Anie: a/d conversion end interrupt enable flag
Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
64
Panasonic
ADM0ICH: Address 0 Match Interrupt Control Register (High)
x’00FC7F’
ADM0ICH enables address match 0 interrupts. It is an 8-bit access regis-
ter. Use the MOVB instruction to access it.
The priority level for address match 0 interrupts is written to the
ADM3LV[2:0] field of the ADM3ICH register.
ADM0IE: Address match 0 interrupt enable flag
0: Disable
1: Enable
ANICL: A/D Conversion End Interrupt Control Register (Low)
x’00FC80’
ANICL detects and requests A/D conversion end interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
ANIR: A/D conversion end interrupt request flag
0: No interrupt requested
1: Interrupt requested
ANID: A/D conversion end interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
ANICH: A/D Conversion End Interrupt Control Register (High)
x’00FC81’
ANICH sets the priority level for and enables A/D conversion end inter-
rupts. It is an 8-bit access register. Use the MOVB instruction to access it.
ANLV[2:0]: A/D conversion end interrupt priority level
Sets the priority from 0 to 6.
ANIE: A/D conversion end interrupt enable flag
0: Disable
1: Enable
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
ADM0
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
ANIR
—
—
—
ANID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
ANLV2
ANLV1
ANLV0
—
—
—
ANIE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R/W
R/W
R
R
R
R/W