Siemens SPC3 - Manual (Page 39)

SPC3 PROFIBUS Interface Center
SPC3 Hardware Description V1.3 Page 37
Copyright (C) Siemens AG 2003 All rights reserved. 2003/04
7 Hardware Interface
7.1 Universal Processor Bus Interface
7.1.1 General Description
SPC3 has a parallel 8-bit interface with an 11-bit address bus. SPC3 supports all 8-bit processors and
microcontrollers based on the 80C51/52 (80C32) from Intel, the Motorola HC11 family, as well as 8-/16-bit
processors or microcontrollers from the Siemens 80C166 family, X86 from Intel, and the HC16 and HC916
family from Motorola. Because the data formats from Intel and Motorola are not compatible, SPC3
automatically carries out ‘byte swapping’ for accesses to the following 16-bit registers (interrupt register,
status register, and mode register0) and the 16-bit RAM cell (R-User_Wd_Value). This makes it possible for
a Motorola processor to read the 16-bit value correctly. Reading or writing takes place, as usual, through
two accesses (8-bit data bus).
Due to the 11-bit address bus, SPC3 is no longer fully compatible to SPC2 (10-bit address bus). However,
AB(10) is located on the XINTCI output of the SPC2 that was not used until now. For SPC3, the AB(10)
input is provided with an internal pull-down resistor. If SPC3 is to be connected into existing SPC2
hardware, the user can use only 1 kByte of the internal RAM. Otherwise, the AB(10) cable on the modules
must be moved to the same place.
The Bus Interface Unit (BIU) and the Dual Port RAM Controller (DPC) that controls accesses to the internal
RAM belong to the processor interface of the SPC3.
In addition, a clock rate divider is integrated that the clock pulse of an external clock pulse generator divided
by 2 (Pin: DIVIDER = High-Potential) or 4 (Pin: DIVIDER = Low-Potential) makes available on the pin
CLKOUT2/4 as the system clock pulse so that a slower controller can be connected without additional
expenditures in a low-cost application. SPC3 is supplied with a clock pulse rate of 48MHz.
7.1.2 Bus Interface Unit (BIU)
The BIU forms the interface to the connected processor/microcontroller. This is a synchronous or
asynchronous 8-bit interface with an 11-bit address bus. The interface is configurable via 2 pins
(XINT/MOT, MODE). The connected processor family (bus control signals such as XWR, XRD, or R_W,
and the data format) is specified with the XINT/MOT pin. Synchronous (rigid) or asynchronous bus timing is
specified with the MODE pin.
Various Intel system configurations are displayed in the figures in Section 7.1.3. The internal address latch
and the integrated decoder must be used in the C32 mode. One figure displays the minimum configuration
of a system with SPC3, whereby the block is connected to an EPROM version of the controller. Only a
pulse generator is necessary as an additional block in this configuration. If a controller is to be used without
an integrated program memory, the addresses must once again be latched off for the external memory.
The connection schematic in the next figure is applicable for all Intel/Siemens processors that offer
asynchronous bus timing and evaluate the ready signal.
Notes:
If the SPC3 is connected to an 80286 processor, or others, it must be taken into consideration that the
processor carries out word accesses. That is, either a “swapper” is necessary that switches the characters
out of the SPC3 at the relevant byte position of the 16-bit data bus during reading, or the least significant
address bit is not connected, and the 80286 must read word accesses and evaluate only the lower byte, as
displayed in the figure.