FUJITSU 2000 - Manual (Page 52)

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• SDRAM CAS latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing. The settings are: 2 and 3.
• SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle. The settings are: 5/7 and
6/8.
• SDRAM RAS-to-CAS Delay
This field lets you inser t a timing delay between the CAS and RAS strobe
signals, used when DRAM is written to, read from, or refreshed. Fast gives
faster per formance; and Slow gives more stable per formance. This field
applies only when synchronous DRAM is installed in the system.
The settings are: 2 and 3.
• SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete and the DRAM
may fail to retain data. Fast gives faster per formance; and Slow gives more
stable per formance. This field applies only when synchronous DRAM is
installed in the system. The settings are: 2 and 3.
• System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh,
resulting in better system per formance. However, if any program writes to this
memor y area, a system error may result. The settings are: Enabled and
Disabled.
• Video BIOS Cacheable
Select Enabled allows caching of the video BIOS , resulting in better system
per formance. However, if any program writes to this memor y area, a system
error may result. The settings are: Enabled and Disabled.
• Memory Hole At 15M-16M
You can reser ve this area of system memor y for ISA adapter ROM. When this
area is reserved, it cannot be cached. The user information of peripherals that
need to use this area of system memory usually discusses their memor y
requirements. The settings are: Enabled and Disabled.
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