Maxim Integrated DS33R11 - Manual (Page 72)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
72 of 344
10 INTEGRATED T1/E1/J1 TRANSCEIVER
10.1 T1/E1/J1 Clocks
Figure 10-1 shows the clock map of the T1/E1 transceiver. The routing for the transmit and receive clocks are
shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator,
which can be placed in the receive or transmit path, two are shown for simplification and clarity.
Figure 10-1. T1/E1/J1 Clock Map
The TCLKT MUX is dependent on the state of the TCSS0 and TCSS1 bits in the TR.CCR1 register and the state of
the TCLKT pin.
TRANSMIT
FORMATTER
RECEIVE
FRAMER
BPCLK
SYNTH
REMOTE
LOOPBACK FRAMER
LOOPBACK PAYLOAD
LOOPBACK
(SEE NOTES)
LTCA
LTCA
JITTER ATTENUATOR
SEE TR.LIC1
REGISTER LOCAL
LOOPBACK
BPCLK
RCLK
TCLKT
MCLK
RXCLK
TXCLK
TO
LIU
LLB = 0
LLB = 1
PLB = 0
PLB = 1
RLB = 1
RLB = 0
FLB = 1
FLB = 0
JAS = 0
AND
DJA = 0
JAS = 1
OR
DJA = 1
JAS = 0
OR
DJA = 1
JAS = 1
AND
DJA = 0
RCL = 1
RCL = 0
DJA = 1
DJA = 0
8XCLK 8 x PLL
PRE-SCALER
TR.LIC4.MPS0
TR.LIC4.MPS1
TR.LIC2.3 2.048 TO 1.544
SYNTHESIZER
B A C
MCLKS = 0
TSYSCLK
MCLKS = 1
TCLKT
MUX