Maxim Integrated DS33R11 - Manual (Page 272)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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Register Name: TR.H1TFBA, TR.H2TFBA
Register Description: HDLC # 1 Transmit FIFO Buffer Available
HDLC # 2 Transmit FIFO Buffer Available
Register Address: 9Fh, Afh
Bit # 7 6 5 4 3 2 1 0
Name TFBA7 TFBA6 TFBA5 TFBA4 TFBA3 TFBA2 TFBA1 TFBA0
Default
0 0 0 0 0 0 0 0
Bits 0 – 7: Transmit FIFO Bytes Available (TFBAO to TFBA7). TFBA0 is the LSB.
Register Name: TR.IBCC
Register Description: In-Band Code Control Register
Register Address: B6h
Bit # 7 6 5 4 3 2 1 0
Name TC1 TC0 RUP2 RUP1 RUP0 RDN2 RDN1 RDN0
Default
0 0 0 0 0 0 0 0
Bits 6 – 7: Transmit Code Length Definition Bits (TC0 to TC1)
TC1 TC0 Length Selected (bits)
0 0 5
0 1 6/3
1 0 7
1 1 16/8/4/2/1
Bits 3 – 5: Receive Up-Code Length Definition Bits (RUP0 to RUP2)
RUP2 RUP1 RUP0 Length Selected (bits)
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8/16
Bits 0 – 2: Receive Down-Code Length Definition Bits (RDN0 to RDN2)
RDN2 RDN1 RDN0 Length Selected (bits)
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8/16