Maxim Integrated DS33R11 - Manual (Page 286)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
286 of 344
Register Name: TR.TSiAF
Register Description: Transmit Si Bits of the Align Frame
Register Address: D2h
Bit
# 7 6 5 4 3 2 1 0
Name TSiF0 TSiF2 TSiF4 TSiF6 TSiF8 TSiF10 TSiF12 TSiF14
Default 0 0 0 0 0 0 0 0
Bit 7: Si Bit of Frame 0 (TSiF0)
Bit 6: Si Bit of Frame 2 (TSiF2)
Bit 5: Si Bit of Frame 4 (TSiF4)
Bit 4: Si Bit of Frame 6 (TSiF6)
Bit 3: Si Bit of Frame 8 (TSiF8)
Bit 2: Si Bit of Frame 10 (TSiF10)
Bit 1: Si Bit of Frame 12 (TSiF12)
Bit 0: Si Bit of Frame 14 (TSiF14)
Register Name:
TR.TSiNAF
Register Description: Transmit Si Bits of the Nonalign Frame
Register Address: D3h
Bit
# 7 6 5 4 3 2 1 0
Name TSiF1 TSiF3 TSiF5 TSiF7 TSiF9 TSiF11 TSiF13 TSiF15
Default 0 0 0 0 0 0 0 0
Bit 7: Si Bit of Frame 1 (TSiF1)
Bit 6: Si Bit of Frame 3 (TSiF3)
Bit 5: Si Bit of Frame 5 (TSiF5)
Bit 4: Si Bit of Frame 7 (TSiF7)
Bit 3: Si Bit of Frame 9 (TSiF9)
Bit 2: Si Bit of Frame 11 (TSiF11)
Bit 1: Si Bit of Frame 13 (TSiF13)
Bit 0: Si Bit of Frame 15 (TSiF15)