Maxim Integrated DS33R11 - Manual (Page 14)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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2.12 T1/E1/J1 Framer
• Fully independent transmit and receive functionality
• Full receive and transmit path transparency
• T1 framing formats include D4 (SLC-96) and ESF
• Detailed alarm and status reporting with optional interrupt support
• Large path and line error counters for:
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T1: BPV, CV, CRC6, and framing bit errors
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E1: BPV, CV, CRC4, E-bit, and frame alignment errors
• Timed or manual update modes
• DS1 idle code generation on a per-channel basis in both transmit and receive paths
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User-defined
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Digital milliwatt
• ANSI T1.403-1998 Support
• RAI-CI detection and generation
• AIS-CI detection and generation
• E1 ETS 300 011 RAI generation
• G.965 V5.2 link detect
• Ability to monitor one DS0 channel in both the transmit and receive paths
• In-band repeating pattern generators and detectors
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Three independent generators and detectors
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Patterns from 1 to 8 bits or 16 bits in length
• RCL, RLOS, RRA, and RAIS alarms interrupt on change-of-state
• Flexible signaling support
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Software or hardware based
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Interrupt generated on change of signaling data
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Receive signaling freeze on loss-of-sync, carrier loss, or frame slip
• Addition of hardware pins to indicate carrier loss and signaling freeze
• Automatic RAI generation to ETS 300 011 specifications
• Access to Sa and Si bits
• Option to extend carrier loss criteria to a 1ms period as per ETS 300 233
• Japanese J1 support
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Ability to calculate and check CRC6 according to the Japanese standard
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Ability to generate Yellow Alarm according to the Japanese standard
2.13 TDM Bus
• Dual two-frame independent receive and transmit elastic stores
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Independent control and clocking
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Controlled slip capability with status
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Minimum delay mode supported
• Programmable output clocks for fractional T1, E1, H0, and H12 applications
• Hardware signaling capability
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Receive signaling reinsertion to a backplane multiframe sync
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Availability of signaling in a separate PCM data stream
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Signaling freezing
• Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode
• Access to the data streams in between the framer/formatter and the elastic stores
• User-selectable synthesized clock output