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Maxim Integrated DS33R11 User Manual

Page 231

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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

231 of 344

Register Name:

TR.PCPR

Register Description:

Per-Channel Pointer Register

Register Address:

28h


Bit

# 7 6 5 4 3 2 1 0

Name RSAOICS RSRCS RFCS BRCS THSCS PEICS TFCS BTCS
Default

0 0 0 0 0 0 0 0


Bit 7: Receive Signaling All-Ones Insertion Channel Select (RSAOICS)


Bit 6: Receive Signaling Reinsertion Channel Select (RSRCS)

Bit 5: Receive Fractional Channel Select (RFCS)

Bit 4: Bert Receive Channel Select (BRCS)

Bit 3: Transmit Hardware Signaling Channel Select (THSCS)

Bit 2: Payload Error Insert Channel Select (PEICS)

Bit 1: Transmit Fractional Channel Select (TFCS)

Bit 0: Bert Transmit Channel Select (BTCS)

See Section

10.2

for a general overview of per-channel operation. See Section

10.10

for more information on per-

channel idle code generation. See Section

10.6

for more information on per-channel loopback operation.