Epson FX-870/1170 - Manual (Page 144)

Principles of Operation
Printhead Drive Circuit
The printhead drive circuit receives two types of signals: image data and the pulse length control
signals. Image data is created in the CPU, transferred to the gate array, and latched to the
printhead. The pulse length control signal is set by the CPU. The pulse length is adjusted referring
to the voltage of the
V line. These two types of signals are sent to the printhead to print each
dot. Figure 6-29 shows the printhead drive circuit.
I
DO-7 DO-7
P51
P83 HPW
HDP
Figure 6-29. Printhead Drive Circuit
Parallel Interface Circuit
The parallel interface circuit controls the data flow from the host computer. When signal
is sent from the host computer, the data is latched into the gate array Data is
transmitted until a BUSY signal is sent back automatically to the host computer to stop the data.
Then, the gate array outputs an
signal to (the interrupt signal port) of the CPU. The CPU
then reads the data latched into the gate array and, on completion reading, resets the BUSY
signal to enable the host computer to send more data. Figure 6-30 shows the parallel interface
circuit.
Parallel I/F
DO-7
STROBE
B U S Y
DINO-7 DATAO-7
STB IBF
- - - - - - - -
I
II
I
BUSY
DO-7
P82
Figure Parallel Interface Circuit
Epson FX-870/1170
6-29