Sundance SMT702 - Manual (Page 7)

1 Introduction
The SMT702 is a PXI Express (opt. Hybrid) Peripheral Module (3U), which integrates
two fast 8-bit ADCs, a clock circuitry, 2 banks of DDR2 Memory (1GByte each), IO
connectors (2 SHBs, SATA and RSL) and a Virtex5 Xilinx FPGA, under the 3U format.
The PXIe specification integrates PCI Express signalling into the PXI standard for
more backplane bandwidth. It also enhances PXI timing and synchronisation
features by incorporating a 100MHz differential reference clock and triggers. The
SMT702 can also integrate the standard 32-bit PXI signalling as an option.
Both ADC chips are identical and can produce 3 Giga-samples per second each, with
an 8-bit resolution. The manufacturer is National Semiconductor and the part
number is ADC083000. Analog-to-Digital converters are clocked by circuitry based
on a PLL coupled with a VCO in order to generate a low-jitter signal. Each ADC
integrates settings such as offset and scale factor, which makes the pair of ADC
suitable to be combined together in order to make a 6GSPS single Analog to Digital
converter. This will be subject to a specific FPGA design.
An on-board PLL+VCO chip ensures a stable fixed sampling frequency (maximum
rate), in order for the board to be used as a digitiser without the need of external
clock signal. The PLL will be able to lock its internal VCO either on the 100MHz PXI
express reference, on the 10MHz PXI reference or on an external reference signal.
The sampling clock for the converters can be either coming from the PLL+VCO chip
(fixed frequency of 1.5ghz) or from an external source. The chip used is a National
Semiconductor part: LMX2531LQ1500. The reference clock selected is also output
on a connector in order to pass it to an other module.
The Virtex5 FPGA is responsible for controlling all interfaces, including PXI (32-bit)
and PXIe (up to 8 lanes – not all PXI Express controller support 8 lane), as well as
routing samples. The FPGA fitted on the SMT702 is part of the Virtex-5 familly from
Xilinx, XC5VLX110T-3 (fastest speed grade available).
Two DDR2 memory banks are accessible by the FPGA in order to store data on the
fly. Each bank can store up to 1GByte.
An SHB connector is available in order to transfer data/samples to an other
Sundance module (SMT712 for instance)
All analog connectors on the front panel are SMA.