Sundance SMT702 - Manual (Page 17)

A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 465 out of 640 72%
Number of LOCed IOBs: 465 out of 465 100%
IOB Flip Flops: 694
IOB Master Pads: 1
IOB Slave Pads: 1
Number of bonded IPADs: 10
Number of LOCed IPADs: 2 out of 10 20%
Number of bonded OPADs: 8
Specific Feature Utilization:
Number of BlockRAM/FIFO: 42 out of 228 18%
Number using BlockRAM only: 26
Number using FIFO only: 16
Total primitives used:
Number of 36k BlockRAM used: 22
Number of 18k BlockRAM used: 4
Number of 36k FIFO used: 14
Number of 18k FIFO used: 2
Total Memory used (KB): 1,404 out of 8,208 17%
Number of BUFG/BUFGCTRLs: 26 out of 32 81%
Number used as BUFGs: 26
Number of IDELAYCTRLs: 6 out of 22 27%
Number of BSCANs: 1 out of 4 25%
Number of BUFDSs: 1 out of 8 12%
Number of BUFIOs: 16 out of 80 20%
Number of DCM_ADVs: 8 out of 12 66%
Number of LOCed DCM_ADVs: 8 out of 8 100%
Number of GTX_DUALs: 2 out of 8 25%
Number of LOCed GTX_DUALs: 2 out of 2 100%
Number of PCIEs: 1 out of 3 33%
Number of LOCed PCIEs: 1 out of 1 100%
Number of PLL_ADVs: 1 out of 6 16%
Number of SYSMONs: 1 out of 1 100%
Number of RPM macros: 137
Average Fanout of Non-Clock Nets: 3.12