Sundance SMT702 - Manual (Page 14)

Number using O5 and O6: 1,625
Number used as Memory: 439 out of 17,920 2%
Number used as Dual Port RAM: 308
Number using O6 output only: 204
Number using O5 output only: 20
Number using O5 and O6: 84
Number used as Shift Register: 131
Number using O6 output only: 131
Number used as exclusive route-thru: 30
Number of route-thrus: 357
Number using O6 output only: 325
Number using O5 output only: 32
Slice Logic Distribution:
Number of occupied Slices: 6,129 out of 17,280 35%
Number of LUT Flip Flop pairs used: 18,945
Number with an unused Flip Flop: 3,691 out of 18,945 19%
Number with an unused LUT: 7,246 out of 18,945 38%
Number of fully used LUT-FF pairs: 8,008 out of 18,945 42%
Number of unique control sets: 812
Number of slice register sites lost
to control set restrictions: 1,801 out of 69,120 2%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
OVERMAPPING of BRAM resources should be ignored if the design is
over-mapped for a non-BRAM resource or if placement fails.
IO Utilization:
Number of bonded IOBs: 463 out of 640 72%
Number of LOCed IOBs: 461 out of 463 99%
IOB Flip Flops: 693
IOB Master Pads: 1
IOB Slave Pads: 1
Number of bonded IPADs: 10 out of 50 20%
Number of bonded OPADs: 8 out of 32 25%
Specific Feature Utilization:
Number of BlockRAM/FIFO: 38 out of 148 25%
Number using BlockRAM only: 22
Number using FIFO only: 16
Total primitives used:
Number of 36k BlockRAM used: 21
Number of 18k BlockRAM used: 1
Number of 36k FIFO used: 14
Number of 18k FIFO used: 2
Total Memory used (KB): 1,314 out of 5,328 24%
Number of BUFG/BUFGCTRLs: 23 out of 32 71%
Number used as BUFGs: 23
Number of IDELAYCTRLs: 6 out of 22 27%
Number of BUFDSs: 1 out of 8 12%
Number of BUFIOs: 16 out of 80 20%
Number of DCM_ADVs: 8 out of 12 66%
Number of LOCed DCM_ADVs: 8 out of 8 100%
Number of GTP_DUALs: 2 out of 8 25%
Number of LOCed GTP_DUALs: 2 out of 2 100%
Number of PCIEs: 1 out of 1 100%
Number of PLL_ADVs: 1 out of 6 16%
Number of SYSMONs: 1 out of 1 100%
Number of RPM macros: 128