Sundance SMT702 - Manual (Page 65)

9 Hardware Modification
It has been found that modifying the converter reset structure improves the
synchronisation between the ADCs. The non-symetrical structure previously used
would add a non-wanted delay on the second ADC channels.
The new structure consists in removing some ICs and replacing them by 2 sets of
differential wires. ADCs can now be more accurately synchronised in frequency. A
software function has been added to the software package, returning the skew
between the 2 ADC sampling clocks. A typical skew measured at the FPGA is 170pS.
Figure 22 - ADC Reset structure modification.