Measurement Computing CIO-DAS16Jr/16 - Manual (Page 23)

COUNTER SECTION
Counter type 82C54
Configuration 3 down counters, 16 bits each
Counter 0 - independent, available to user
Source: programmable: external (CTR0 Clock In) or 100 kHz internal
Gate:
programmable: external (Dig In 2 / Ctr 0 Gate, active high) or disabled
Output: Available at user connector (CTR 0 Out)
Counter 1 - ADC Pacer Lower Divider
Source: 10 MHz internal
Gate:
Tied to Counter 2 gate, programmable source: internal or external (DIG. IN
0 / TRIGGER).
Output: Chained to Counter 2 Clock.
Counter 2 - ADC Pacer Upper Divider
Source: Counter 1 Output.
Gate:
Tied to Counter 1 gate, programmable source: internal or external (DIG. IN
0 / TRIGGER).
Output: ADC Pacer clock, available at user connector (CTR 2 Out)
Clock input frequency 10 Mhz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min
Crystal oscillator
Frequency 10 MHz
Frequency accuracy 100 ppm
ENVIRONMENTAL
Operating temperature range 0 to 50°C
Storage temperature range
−
20 to 70°C
Humidity 0 to 90% non-condensing
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