Measurement Computing CIO-DAS6402/12 - Manual (Page 36)

Counter section
Counter type 82C54
Configuration 3 down-counters, 16 bits each
Counter 0
Compatible mode - Independent
Source: Programmable external (CTR0 CLK) or 100kHz internal source).
Gate:
Available at connector (DIN2).
Output: Available at connector (CTR0 OUT).
Enhanced mode - ADC residual sample counter
Source: ADC Clock.
Gate:
Internal use.
Output: End-of-Acquisition interrupt.
Counter 1 - ADC Pacer Lower Divider
Source: 10 MHz oscillator
Gate:
Tied to Counter 2 gate, programmable source.
Output: Chained to Counter 2 Clock.
Counter 2 - ADC Pacer Upper Divider
Source: Counter 1 Output.
Gate:
Tied to Counter 1 gate, programmable source.
Output: ADC Pacer clock, available at user connector.
Clock input frequency 10 MHz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min
Environmental
Operating temperature range 0 to 70°C
Storage temperature range - 40 to 100°C
Humidity 0 to 90% non-condensing
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