Measurement Computing CIO-DAS6402/12 - Manual (Page 34)

8.2 CIO-DAS6402/12
Typical for 25°C unless otherwise specified.
Power consumption
Icc: Operating 1.05 A typical, 1.6 A max
Analog input section
A/D converter type ADS7800, Successive Approximation
Resolution 12 bits
Programmable ranges ±10V, ±5V, ±2.5V, ±1.25V, 0 to 10V, 0 to 5V, 0 to 2.5V, 0 to 1.25V
A/D pacing Programmable: internal counter or external source (DIN0, rising edge)
Data transfer Compatible: Byte wide, interrupt, software polled, DMA
Enhanced: Word wide, interrupt, software polled, REP INSW
Above via 1k sample FIFO
Burst Mode (programmable option) @ 250 kHz
Polarity Unipolar/Bipolar, software-selectable
Number of channels Compatible: 8 differential or 16 single-ended, software-selectable
Enhanced: 32 differential or 64 single-ended, software-selectable
Interrupts Programmable levels 2, 3, 5, 7, 10, 11, 15
Positive-edge triggered
Interrupt enable Programmable interrupt enable for internal and external interrupt
Interrupt sources End-of-conversion, FIFO not empty, FIFO half full, end-of-burst, external
Trigger sources Compatible: External hardware/software (DIN0)
Enhanced: External trigger/gate (DIN1), edge/level, polarity/edge programmable.
A/D Triggering Modes Digital:
Software configurable for Edge (triggered) or level-activated (gated).
Programmable polarity (rising/falling edge trigger, high/low gate).
Pre-trigger:
Unlimited pre- and post-trigger samples. Total # of samples must be > 512.
A/D conversion time 3 µs
Throughput 333 kHz min
Differential Linearity error ±.75 LSB
Integral Linearity error ±.5 LSB
No missing codes guaranteed 12 bits
Gain drift (A/D specs) ±6 ppm/°C, all ranges
Zero drift (A/D specs) ±1 ppm/°C, all ranges
Input leakage current (@25 Deg C) 200 nA
Input impedance Min 10Meg Ohms
Absolute maximum input voltage ±15V
30