BECKHOFF ET9300 - Manual (Page 16)

14 Application Note ET9300
Table 2: Recommended Hardware Configurations
Platform
E
L
9
8
0
0
_
HW
P
IC
2
4
P
IC
1
8
MCI_H
W
FC
1
1
0
0
_
H
W
C
ON
TR
OL
L
E
R
_
1
6
B
IT
C
ON
TR
OL
L
E
R
_
3
2
B
IT
E
S
C
_
1
6
B
IT_AC
C
E
S
S
E
S
C
_
3
2
B
IT_AC
C
E
S
S
MB
X
_
1
6
B
IT_AC
C
E
S
S
B
IG_
E
N
D
IA
N
_
1
6
B
IT
B
IG_
E
N
D
IA
N
_
FOR
MA
T
Comment
Microchip PIC18F452
Generic : 8Bit µC ; SPI ESC
access 1 0 1 0 0 0 0 0 0 0 0 0 The stack is ready to use if the PIC 18 on the EL9800 EtherCAT Evaluation board
is used. Otherwise there might be requirements to adapt the hardware access
Microchip
PIC24HJ128GP306
Generic: 16Bit µC; SPI ESC
access 1 1 0 0 0 1 0 1 0 1 0 0 The stack is ready to use if the PIC 24 on the EL9800 EtherCAT Evaluation board
is used. Otherwise there might be requirements to adapt the hardware access.
x86
(OS Windows) 0 0 0 0 1 0 1 0 1 0 0 0 The stack is ready to use if the stack shall run on a Win32 OS in user mode.
Otherwise changes in hardware access might be required.
The setting “FC1100_HW” is a adapted implementation based on “MCI_HW
Texas Instruments Sitara
AM335x 0 0 0 0 0 0 0 0 0 0 0 0 To use the SSC on TI AM335x chips the hardware access files from the TI SDK
need to be added to the project. The files can be added to the slave project via the
patch file (delivered with the SDK), by selecting the TI configuration in the SSC
Tool or by adding the files manually.
Altera® NIOS®II
(ESC connected via Avalon
bus) 0 0 0 1 0 x x x x x 0 0 x: depends on the NIOS® configuration in the SOPC builder.
In general the following points need to be adapted:
-
define “MAKE_PTR_TO_ESC”
- ISRs for Timer/PDI interrupt and Sync0 (depends on the supported features)
- Implement timer access functions and macros
Depending on the platform configuration further changes may be required.