Zilog Z8PE002 - Manual (Page 22)

Z8PE002
Z8Plus OTP Microcontroller ZiLOG
22 P R E L I M I N A R Y DS008700-Z8X0799
Note: The WDT can only be disabled via software if the first in-
struction out of the RESET performs this function. Logic
within the device detects that it is in the process of exe-
cuting the first instruction after the processor leaves
RE-
SET . During the execution of this instruction, the upper
five bits of the TCTLHI register can be written. After this
first instruction, hardware does not allow the upper five
bits of this register to be written.
The TCTLHI bits for control of the WDT are described be-
low:
WDT Time Select (D6, D5, D4). Bits 6, 5, and 4 determine
the time-out period. Table 13 indicates the range of time-
out values that can be obtained. The default values of
D6 ,
D5 , and D4 are 001 , which sets the WDT to its minimum
time-out period when coming out of RESET .
WDT During HALT (D7). This bit determines whether or
not the WDT is active during HALT mode. A 1 indicates ac-
tive during HALT mode. A 0 prevents the WDT from reset-
ting the part while halted. Coming out of RESET , the WDT
is enabled during HALT mode.
STOP MODE (D3). Coming out of RESET , the device
STOP mode is disabled. If an application requires use of
STOP mode, bit D3 must be cleared immediately at leaving
RESET . If bit D3 is set, the STOP instruction executes as a
NOP . If bit D3 is cleared, the STOP instruction enters STOP
mode.
Bits 2, 1 and 0. These bits are reserved and must be 0 .
POWER-DOWN MODES
In addition to the standard RUN mode, the Z8Plus MCU
supports two Power-Down modes to minimize device cur- rent consumption. The two modes supported are HALT and
STOP .
HALT MODE OPERATION
The HALT mode suspends instruction execution and turns
off the internal CPU clock. The on-chip oscillator circuit
remains active so the internal clock continues to run and is
applied to the timers and interrupt logic.
To enter HALT mode, the device only requires a HALT in-
struction. It is not necessary to execute a NOP instruction
immediately before the HALT instruction.
HALT mode can be exited by servicing an external or inter-
nal interrupt. The first instruction executed is the interrupt
service routine. At completion of the interrupt service rou-
tine, the user program continues from the instruction after
the
HALT instruction.
The HALT mode can also be exited via a RESET activation
or a Watch-Dog Timer ( WDT ) time-out. In these cases, pro-
gram execution restarts at 0020H , the reset restart address.
Table 13. WDT Time-Out
D6 D5 D4
Crystal Clocks*
to Timeout Time-Out Using
a 10-MHz Crystal
0 0 0 Disabled Disabled
0 0 1 65,536 TpC 6.55 ms
0 1 0 131,072 TpC 13.11 ms
0 1 1 262,144 TpC 26.21 ms
1 0 0 524,288 TpC 52.43 ms
1 0 1 1,048,576 TpC 104.86 ms
1 1 0 2,097,152 TpC 209.72 ms
1 1 1 8,388,608 TpC 838.86 ms
Note: *TpC is an XTAL clock cycle. The default at reset is 001.
7F HALT ; enter HALT mode