Altera Transceiver Signal Integrity Development Kit, Stratix V GT Edition - Manual (Page 29)

Chapter 2: Board Components 2–21
Clock Circuitry
May 2014 Altera Corporation Transceiver Signal Integrity Development Kit
Stratix V GT Edition Reference Manual
Clock Circuitry
This section describes the board's dedicated and general purpose clocks.
Dedicated Transceiver Clocks
Four differential clock sources are provided from the I 2 C programmable VCO
oscillators to the dedicated REFCLK input pins of transceiver blocks on both sides of
the FPGA. The default frequencies for these four oscillators at startup are 625 MHz,
644.53125 MHz, 706.25 MHz, and 875 MHz. The default frequencies can be
overridden and you can program a different frequency into the oscillators to support
other protocols. Each oscillator supports a programmable frequency range of
10 MHz–1.4 GHz and provides a trigger output to an SMA connector for scope or
other lab equipment triggering purposes.
Figure 2–6 shows the default frequencies of all external clocks going to the
Stratix V GT transceiver signal integrity development board.
Table 2–14 lists the frequency of these oscillators and the application it supports.
Figure 2–6. Transceiver Signal Integrity Development Kit Dedicated Transceiver Clocks
6-12.5G
Channels
Clock
Buffer
6-12.5G
Channels
6-12.5G
Channels
6-12.5G
Channels
2-12.5G
Channels
+
1-28G
Channel
2-12.5G
Channels
+
1-28G
Channel
2-12.5G
Channels
+
1-28G
Channel
2-12.5G
Channels
+
1-28G
Channel
644.53125 MHz Trigger
Trigger
Clock
Buffer
706.25 MHz Trigger
Clock
Buffer
625 MHz
Trigger
SMA
REFCLK
Stratix V GT FPGA
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
REFCLK
Clock
Buffer
875 MHz
SMA
Table 2–14. Transceiver On-Board Oscillators
Frequency i/O Standard Clock Buffer
644.53125 MHz LVDS IDT5T9306
625 MHz LVDS IDT5T9306
706.25 MHz LVDS IDT5T9306
875 MHz LVDS IDT5T9306