Altera Transceiver Signal Integrity Development Kit, Stratix V GT Edition - Manual (Page 18)

2–10 Chapter 2: Board Components
MAX II CPLD System Controller
Transceiver Signal Integrity Development Kit May 2014 Altera Corporation
Stratix V GT Edition Reference Manual
CONFIG_D2 P12 AT32 2.5-V Configuration data
CONFIG_D3 P11 AW32 2.5-V Configuration data
CONFIG_D4 R11 AV32 2.5-V Configuration data
CONFIG_D5 R10 AM32 2.5-V Configuration data
CONFIG_D6 N12 AL31 2.5-V Configuration data
CONFIG_D7 P10 AN32 2.5-V Configuration data
CONFIG_D8 H4 AN31 2.5-V Configuration data
CONFIG_D9 J4 AM31 2.5-V Configuration data
CONFIG_D10 J3 AL30 2.5-V Configuration data
CONFIG_D11 K2 AK30 2.5-V Configuration data
CONFIG_D12 K5 AJ30 2.5-V Configuration data
CONFIG_D13 K4 AJ29 2.5-V Configuration data
CONFIG_D14 K3 AJ28 2.5-V Configuration data
CONFIG_D15 L5 AM29 2.5-V Configuration data
CONFIG_ERR R9 — 2.5-V Configuration error
DCLK T8 U28 2.5-V Configuration clock
ENET_RSTn A15 AT6 2.5-V Ethernet LED
F_AD1 M16 AE14 2.5-V Flash address bus
F_AD2 M15 AD14 2.5-V Flash address bus
F_AD3 M14 AC13 2.5-V Flash address bus
F_AD4 N16 AC12 2.5-V Flash address bus
F_AD5 N15 AG14 2.5-V Flash address bus
F_AD6 J16 AF14 2.5-V Flash address bus
F_AD7 N13 AD11 2.5-V Flash address bus
F_AD8 N14 AC11 2.5-V Flash address bus
F_AD9 C14 AF11 2.5-V Flash address bus
F_AD10 B12 AE11 2.5-V Flash address bus
F_AD11 F15 AE13 2.5-V Flash address bus
F_AD12 F16 AE12 2.5-V Flash address bus
F_AD13 D16 AJ14 2.5-V Flash address bus
F_AD14 A11 AH13 2.5-V Flash address bus
F_AD15 A12 AG13 2.5-V Flash address bus
F_AD16 B13 AF13 2.5-V Flash address bus
F_AD17 E15 AJ13 2.5-V Flash address bus
F_AD18 L14 AJ12 2.5-V Flash address bus
F_AD19 J15 AH12 2.5-V Flash address bus
F_AD20 D14 AG11 2.5-V Flash address bus
F_AD21 K14 AK12 2.5-V Flash address bus
F_AD22 D15 AK11 2.5-V Flash address bus
Table 2–5. MAX II CPLD System Controller Device Pin-Out (Part 2 of 5)
Schematic Signal
Name
MAX II CPLD
Pin Number
Stratix V GT
Pin Number
I/O
Standard
Description