Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board User Manual
Page 33
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Altera Corporation
Reference Manual
2–23
May 2006
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board
Board Components & Interfaces
Table 2–14
lists the S7 output clock DIP switch settings.
Figure 2–15
shows the DIP switch board image.
Figure 2–15. DIP Switch Board Image
lists the S8 output clock DIP switch settings.
Table 2–14. User-Defined DIP Switch Pinout (S7)
S7 Switch
Stratix II GX Pin
S7_1
AH33
S7_2
AH32
S7_3
AF28
S7_4
AF27
S7_5
AJ34
S7_6
AJ33
S7_7
AG29
S7_8
AG28
Table 2–15. Output Clock Setting DIP Switch Pinout (S8)
Switch
25 MHz
100 MHz
125 MHz
200 MHz
SW1
Closed
Open
Closed
Open
SW2
Closed
Closed
Open
Open
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