Altera Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board - Manual (Page 22)

2–12 Reference Manual Altera Corporation
Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board May 2006
Interfaces
Interfaces This section describes the Stratix II GX EPS2GX90 transceiver signal
integrity development board’s interface architecture. There are three
main interface blocks:
■ SMA connectors for high-speed I/O
■ USB interface
■ General user interfaces
SMA Connectors for High-Speed I/O
The Stratix II GX EPS2GX90 transceiver signal integrity development
board has SMA connectors supporting the most commonly-used, high-
speed interface protocols. The SMA connectors are helpful for equipment
testing. The board has six channels of transmit (TX) differential output as
well as six channels of receive (RX) differential input running at up to
6.375 Gbps. See
Figure 2–6 .
Table 2–7 lists the SMA-to-FPGA pinout table.
Table 2–7. SMA-to-FPGA Pinout Table
SMA Board
Reference
Schematic Signal Name
Stratix II GX (U20)
Pin Number
J7 REFCLKOP_QUAD1 G1
J8 REFCLKON_QUAD1 G2
J9 REFCLKOP_QUAD3 AK4
J10 REFCLKON_QUAD3 AK5
J11 CLOCKOUT_P AP17
J12 GLK_P AP18
J13 CLOCKOUT_N AN17
J14 GCLK_N AP19