Altera Nios Development Board Stratix II Edition - Manual (Page 41)

Altera Corporation Reference Manual 2–31
May 2007 Nios Development Board Stratix II Edition
Board Components
Table 2–16 shows the pin out information for J25.
Test Points
(TP1 – TP8) TP1 – TP8 are test points connected to I/O pins on the FPGA. FPGA
designs can route signals to these I/O pins to be probed. TP1 –TP8 also
connect to the configuration controller (U3).
Table 2–16. Mictor Connector Pin Table
FPGA Pin J25 Pin Board Net Name
AD15 5 mictor_clk
T4 38 mictor0
T5 36 mictor1
U3 34 mictor2
U4 32 mictor3
T8 30 mictor4
T9 28 mictor5
V3 26 mictor6
V4 24 mictor7
U5 22 mictor8
U6 20 mictor9
T6 18 mictor10
T7 16 mictor11
U7 10 mictor12
U8 8 mictor13
V5 37 mictor14
V6 35 mictor15
V7 33 mictor16
V8 31 mictor17
WW5 29 mictor18
W6 27 mictor19
W 25 mictor20
W8 23 mictor21
AA5 13 mictor22
AA6 9 mictor23
Y6 7 mictor24
R1 6 mictor_trclk