Altera Nios Development Board Stratix II Edition User Manual
Page 20
2–10
Reference Manual
Altera Corporation
Nios Development Board Stratix II Edition
May 2007
Board Components
f
See www.micron.com for detailed information.
A7
62
sdram_dq13
C7
63
sdram_dq14
D7
65
sdram_dq15
C9
16
sdram_dqs0
C6
51
sdram_dqs1
C10
20
sdram_dm0
B7
47
sdram_dm1
B10
29
sdram_a0
B9
30
sdram_a1
B8
31
sdram_a2
B6
32
sdram_a3
C5
35
sdram_a4
E11
36
sdram_a5
E10
37
sdram_a6
E9
38
sdram_a7
E8
39
sdram_a8
E7
40
sdram_a9
F11
28
sdram_a10
F10
41
sdram_a11
F8
42
sdram_a12
F10
26
sdram_ba0
G11
27
sdram_ba1
B3
22
sdram_cas_n
F13
44
sdram_cke
E12
24
sdram_cs_n
A3
23
sdram_ras_n
B4
21
sdram_we_n
C4
46
sdram_clk_n
C3
45
sdram_clk_p
Table 2–7. DDR SDRAM Pin Table (Continued)
FPGA Pin
U63 Pin
Board Net Name
See also other documents in the category Altera Measuring instruments:
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
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- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)