Altera Nios Development Board Stratix II Edition User Manual
Page 37

Altera Corporation
Reference Manual
2–27
May 2007
Nios Development Board Stratix II Edition
Board Components
Figure 2–11. PMC Connector
The PMC connector supplies +3.3 V, +5.0 V and ±12. V, as required by the
PCI specification. However, DC power regulators for these supplies
cannot provide enough power to fully satisfy the PCI power specification.
The current that the board can supply through JH1 and JH2 is dependent
on the design configured in the FPGA. As a general guideline, if the PMC
card power requirements exceed the specifications shown in
you must connect an external power source.
w
When connecting an external power supply, the fuse for the
corresponding voltage should be removed from the
development board to prevent the two power supplies from
interfering with each other. Refer to
Table 2–14. PMC Card Power Specifications
DC Supply
Maximum Power
Apply External Power Source
+3.3V
9.5 Watts
J29
+5V
15 Watts
J28
+12V
45 Watts
J31
-12V
1.2 Watts
TP13
Pin 1
Pin 1
JH2
JH1
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)