Altera Nios Development Board Stratix II Edition User Manual
Page 38

2–28
Reference Manual
Altera Corporation
Nios Development Board Stratix II Edition
May 2007
Board Components
lists the connections between the PMC connector and the
FPGA.
Table 2–15. PMC Connector Pin Table
FPGA Pin
JH1 & JH2 Pin
Connector
Board Net Name
AF22
61
JH1
pmc_ad0
AE22
60
JH1
pmc_ad1
AD22
59
JH1
pmc_ad2
AF21
58
JH1
pmc_ad3
AD21
55
JH1
pmc_ad4
AF20
54
JH1
pmc_ad5
AD20
53
JH1
pmc_ad6
AF19
51
JH2
pmc_ad7
AE19
49
JH2
pmc_ad8
AD19
49
JH1
pmc_ad9
AF18
48
JH2
pmc_ad10
AC18
48
JH1
pmc_ad11
Y18
47
JH1
pmc_ad12
AF17
46
JH2
pmc_ad13
AC17
45
JH2
pmc_ad14
Y17
46
JH1
pmc_ad15
AE16
31
JH2
pmc_ad16
AD16
32
JH1
pmc_ad17
AB16
29
JH2
pmc_ad18
AA16
29
JH1
pmc_ad19
Y16
28
JH2
pmc_ad20
AF10
28
JH1
pmc_ad21
AD10
27
JH1
pmc_ad22
AF9
26
JH2
pmc_ad23
AC9
23
JH2
pmc_ad24
AC8
23
JH1
pmc_ad25
AF7
22
JH2
pmc_ad26
AE6
22
JH1
pmc_ad27
AF5
21
JH1
pmc_ad28
AE5
20
JH2
pmc_ad29
AE4
19
JH2
pmc_ad30
AD4
20
JH1
pmc_ad31
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)