Altera Nios Development Board - Manual (Page 9)

Altera Corporation 1–1
December 2004
Board Components
Features ■ A Cyclone TM EP1C20F400C7device
■ 8 Mbytes of flash memory
■ 1 Mbyte of static RAM
■ 16 Mbytes of SDRAM
■ On-board logic for configuring the Cyclone device from flash
memory
■ EPCS4 serial configuration device
■ On-board Ethernet MAC/PHY device
■ Two 5-V-tolerant expansion/prototype headers each with access to
41 Cyclone user I/O pins
■ CompactFlash TM connector header for Type I CompactFlash (CF)
cards
■ Mictor connector for hardware and software debug
■ Two RS-232 DB9 serial ports
■ Four push-button switches connected to Cyclone user I/O pins
■ Eight LEDs connected to Straix user I/O pins
■ Dual 7-segment LED display
■ JTAG connectors to Altera devices via Altera download cables
■ 50 MHz Oscillator and zero-skew clock distribution circuitry
■ Power-on reset circuitry
General
Description The Nios development board, Cyclone Edition, provides a hardware
platform for developing embedded systems based on Altera Cyclone
devices. The Nios development board features a Cyclone EP1C20F400C7
device with 20,060 logic elements (LEs) and 294, 912 bits of on-chip
memory.
The Nios development board comes pre-programmed with a Nios II
processor reference design. Hardware designers can use the reference
design as an example of how to use the features of the Nios development
board. Software designers can use the pre-programmed Nios II processor
design on the board to begin prototyping software immediately.
This document describes the hardware features of the Nios development
board, including detailed pin-out information, to enable designers to
create custom FPGA designs that interface with all components on the
board.