Altera Nios Development Board - Manual (Page 21)

Altera Corporation 1–13
December 2004 Nios Development Board Reference Manual, Cyclone Edition
Board Components
Figure 1–6. Expansion Prototype Connector - J12
Figure 1–7. Expansion Prototype Connector - J13
Notes to Figure 1–7 :
(1) Unregulated voltage from AC to DC power transformer
(2) Clk from board oscillator
(3) Clk from FPGA via buffer
(4) Clk output from protocard to FPGA
Expansion
Prototype
Connector
(PROTO2) Headers J15, J16, and J17 collectively form the standard-footprint,
mechanically-stable connection that can be used (for example) as an
interface to a special-function daughter card.
The expansion prototype connector interface includes:
■ 41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins
on the Cyclone device. Each signal passes through analog switches
(U27, U28, U29, U30 and U31) to protect the Cyclone device from 5-
V logic levels. These analog switches are permanently enabled.
■ A buffered, zero-skew copy of the on-board OSC output (from U2).
■ A buffered, zero-skew copy of the Cyclone's phase-locked loop
(PLL)-output (from U60)
■ A logic-negative power-on-reset signal