Altera Nios Development Board - Manual (Page 29)

Altera Corporation 1–21
December 2004 Nios Development Board Reference Manual, Cyclone Edition
Board Components
Reset Distribution
The EPM7128AE takes a power-on reset pulse from the Linear
Technologies 1326 power-sense/reset-generator chip and distributes it
(through internal logic) to other reset pins on the board, including the:
■ LAN91C111 (Ethernet MAC/PHY) reset
■ Flash memory reset
■ Reset signals delivered to the expansion prototype connectors
(PROTO1 & PROTO2)
Starting Configuration
There are four methods to start a configuration sequence. The four
methods are the following:
1. Board power-on.
2. Pressing the Power-On Reset button (SW10).
3. Asserting (driving 0 volts on) the EPM7128AE's reconfigreq_n
input pin (from a Cyclone design).
4. Pressing the Force Safe button (SW9).
Cyclone Configuration
At power-up or reset, the configuration controller attempts to configure
the Cyclone device with data from one of three sources, in the following
order:
1. The EPCS4 serial configuration device
2. The User configuration from flash memory
3. The Safe configuration from flash memory
First, the configuration controller puts the Cyclone FPGA in active serial
(AS) configuration mode. The Cyclone FPGA will then attempt to read
configuration data from the EPCS4. If the Cyclone FPGA is successfully
configured, the configuration controller stops.
If configuration from the EPCS4 was not successful, the configuration
controller puts the Cyclone FPGA into passive serial mode and attempts
to load the user configuration from flash memory. If this also fails, the
configuration controller attempts to load the safe configuration in flash
memory.