Altera Nios Development Board - Manual (Page 53)

Altera Corporation Index–1
December 2004
Index
A
Appendix A
Shared bus table A–1
Appendix C
Connecting to the Board via Ethernet C–1
B
Block diagram 1–2
Board Ethernet connection
Browse the board C–5
Connecting the Ethernet cable C–1
Connecting the LCD display C–2
Obtaining an IP Address C–2
C
Clock circuitry 1–28
CompactFlash connector 1–6
Configuration and reset buttons 1–26
SW10 - Reset config 1–27
SW8 - CPU reset 1–26
SW9 - Safe config 1–27
Configuration controller device 1–20
Configuration data 1–22
Configuration-status LEDs 1–25
Cyclone configuration 1–21
Reset distribution 1–21
Safe and user configurations 1–22
Starting configuration 1–21
Configuration-status LEDs
Indicators 1–26
Conventional flash memory usage 1–23
Cyclone EP1C20 device 1–4
D
Development board
Features 1–1
General description 1–1
Dual 7-segment display 1–18
U8 & U9 pin information 1–18
Dual SRAM devices 1–10
E
Ethernet PHY/MAC 1–11
Expansion connector header (PROTO1) 1–11
J11 pin information 1–12
J12 pin information 1–13
J13 pin information 1–13
Expansion connector header (PROTO2) 1–13
J15 pin information 1–15
J16 pin information 1–14
J17 pin out information 1–15
F
Flash memory allocation 1–23
Flash memory device 1–5
I
Individual LEDs (D0 - D7) 1–19
Pin information 1–19
J
JTAG connections
JTAG to Cyclone device (J24) 1–29
JTAG to MAX device (J5) 1–30
JTAG connectors 1–29
M
Mictor connector 1–15
Debug port to OCI debug module 1–16
J25 pin information 1–17