Altera Nios Development Board - Manual (Page 31)

Altera Corporation 1–23
December 2004 Nios Development Board Reference Manual, Cyclone Edition
Board Components
When SW9 (Force Safe) is pressed, the configuration controller will ignore
the user configuration and always configure the Cyclone device from the
safe configuration. This switch allows you to “escape” from the situation
where a valid-but-nonfunctional user configuration is present in flash
memory or the serial configuration device.
Using Conventional Flash Memory
The Nios development board includes an 8 MByte flash-memory device
(U5). See
Table 1–6 . It is divided into 128 individually-erasable 64K
sectors. The factory-programmed design, and (more importantly) the on-
board configuration controller, makes certain assumptions about
what–resides–where in flash memory.
In the factory-programmed state, the upper four (4) MBbytes of flash
memory are used to store either FPGA configuration data or web-page
data. Your application software may safely use the lower half (4 MBytes)
of flash memory without interfering with FPGA configuration or web-
server operation.
1 The factory-programmed reference design implements a web
server. Network settings and web pages are pre-programmed in
the flash memory, as shown in
Table 1–7 on page 1–25 .
User Hardware Image
At power on, or when the Power-On Reset button (SW10) is pressed, the
configuration controller begins reading user configuration data out of
flash at address 0x600000. This data, and suitable control signals, are used
in an attempt to configure the FGPA. FPGA configuration data written
into this region of flash memory is conventionally called the user
Table 1–6. Flash Memory Allocation
Address (hex) Flash Allocation
000000 4MB
100000
200000
300000
400000 Web Pages (2MB)
500000
600000 User Configuration Data (1 MB)
700000 Safe Configuration Data (1 MB)