Dual sram devices, Dual sram devices –10 – Altera Nios Development Board User Manual
Page 18
1–10
Altera
Corporation
Nios Development Board Reference Manual, Cyclone Edition
December 2004
Dual SRAM Devices
f
See www.micron.com for detailed SDRAM information.
Dual SRAM
Devices
U35 and U36 are two 512 Kbyte x 16-bit asynchronous SRAM devices.
They are connected to the Cyclone device so they can be used by a Nios II
embedded processor as general-purpose memory. The two 16-bit devices
can be used in parallel to implement a 32-bit wide memory subsystem.
DQ16
31
P4
DQ17
33
R1
DQ18
34
R2
DQ19
36
R6
DQ20
37
R5
DQ21
39
R3
DQ22
40
R4
DQ23
42
T4
DQ24
45
T2
DQ25
47
T3
DQ26
48
U1
DQ27
50
U4
DQ28
51
U2
DQ29
53
U3
DQ30
54
V3
DQ31
56
V2
DQM0
16
J2
DQM1
71
J1
DQM2
28
H4
DQM3
59
H3
RAS_N
19
H2
CAS_N
18
G3
CKE
67
G7
CS_N
20
G6
WE_N
17
G4
CLK
68
L13
Table 1–3. SDRAM (U57) Pin Table (Part 2 of 2)
Pin Name
Pin Number
Connects to Cyclone Pin
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)