Introduction, Appendix a. pin connections hsmc – Altera LCD Multimedia HSMC User Manual
Page 45

Altera Corporation
Development Board Version 1.0.
A–1
August 2008
Preliminary
Appendix A. Pin Connections
HSMC
.FPGA for the
Cyclone III Starter Board
Introduction
The section describes the HSMC pin connections for Cyclone III Starter
Board. See
Tables A–2
Special caution when building applications with the LCD Multimedia
HSMC and the Cyclone III FPGA Starter Board:
c
The LCD Multimedia HSMC uses the differential pair
HSMC_CLKIN pins as single-ended I/O. On the Cyclone III
Starter Board, the n and p signals for these pins are terminated
with 100 Ohm resistors (R3 and R4).
These signals correspond to single-ended I/O on the LCD
Multimedia HSMC. R3 connects HC_RX_CLK and
HC_TD_27MHZ and R4 connects HC_ADC_PENIRQ_n and
HC_TX_CLK. To avoid unwanted noise on signals, users are
advised to turn off the peripherals as shown in the
below.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)