Altera LCD Multimedia HSMC User Manual
Page 17

2–9
Altera Corporation
LCD Multimedia HSMC
August 2008
Level Translator
shows the pinouts of Level Shift Inteface with HSMC connector.
shows the Level Shift Interface schmeatic.
Figure 2–5. Level Shift Interface Schematic
Table 2–6. Level Shift Interface Pinouts with HSMC Connector
HSMC Side Signal
Name
HSMC Pin
No.
Device Side
Signal
Level Shift
Interface Pin No.
Level Shift Interface Description
HC_I2C_SDAT
33
I2C_SDAT
U1-27;U8-33
Audio CODEC ADC LR Clock
HC_PS2_CLK
43
PS2_CLK
J9-6
PS/2 Clock
HC_PS2_DAT
47
PS2_DAT
J9-1
PS/2 Data
HC_MDIO
49
MDIO
U2-30
Ethernet PHY Management Data I/O
HC_SD_DAT3
53
SD_DAT3
J4-1
SD 1-bit Mode: Card Detect; SPI Mode:
Chip Select (Active Low)
HC_SD_CMD
44
SD_CMD
J4-2
SD 1-bit Mode: Command Line; SPI
Mode: Data In
HC_SD_DAT
48
SD_DAT
J4-7
SD 1-bit Mode: Data Line; SPI Mode:
Data Out
HC_SDA
50
SDA
J10-44
LCD 3-Wire Serial Interface Data
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)