Overview, General description, Chapter 1. overview – Altera LCD Multimedia HSMC User Manual
Page 4
Altera Corporation
1–1
August 2008
Preliminary
1. Overview
General
Description
This manual provides comprehensive information about the LCD
Multimedia High Speed Mezzanine Card (HSMC). This HSMC is a full-
featured multimedia board that can be used for video, audio, and
ethernet applications with many of the Altera FPGA Starter and
Development boards that support the HSMC connectors. For example,
see
.
The LCD Multimedia HSMC was created to provide a set of interfaces
including LCD touchscreen, VGA out, composite video in, audio in/out,
microphone in, plus Ethernet, SD-Card, PS/2, and RS-232 interfaces. The
purpose of this reference manual is to describe each of these hardware
interfaces on the LCD HSMC.
f
For the latest information about available HSMC boards, go to
Figure 1–1. LCD Multimedia HSMC in Nios II Embedded Evaluation Kit
The top view of the LCD Multimedia HSMC is shown in
Figure 1–2
.
Cyclone III FPGA Starter Board
LCD Multimedia HSMC
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)