Altera LCD Multimedia HSMC User Manual
Page 21

2–13
Altera Corporation
LCD Multimedia HSMC
August 2008
Display
Figure 2–8
shows the LCD Touch Panel schematic.
HC_SDA
50
U11-5
(
U11-10
)
SDA
J10.44
LCD 3-Wire Serial
Interface Data
HC_ADC_DCLK
157
B18
L3
ADC_DCLK
U6.16
AD7843/LCD 3-Wire Serial
Interface Clock
HC_ADC_DIN
155
B16
N2
ADC_DIN
U6.14
AD7843 Serial Interface
Data In
HC_ADC_CS_n
143
D18
N1
ADC_CS_n
U6.15
AD7843 Serial Interface
Chip Select Input
HC_ADC_DOUT
122
E13
M1
ADC_DOUT
U6.12
AD7843 Serial Interface
Data Out
HC_ADC_PENIRQ_n
156
A14
M3
ADC_PENIRQ_n
U6.11
AD7843 pen Interrupt
HC_ADC_BUSY
120
E15
M2
ADC_BUSY
U6.13
AD7843 Serial Interface
Busy
Notes to
Table 2–8
:
(1)
These signals do not go through the MAX II chip. They pass through the MAX3378 level translator chip, U11.
Table 2–8. LCD Touch Panel Pinout with HSMC Connector
HSMC Connector
MAX II
LCD Touch Panel
Signal Name
Pin
No.
HSMC
Connector
Side Pin
Device
Side Pin
Signal Name
Pin No.
Description
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)