Altera LCD Multimedia HSMC - Manual (Page 28)

Altera Corporation 2–20
August 2008 LCD Multimedia HSMC
Board Components and Interfaces
Figure 2–11 shows the Ethernet PHY connector schematic.
HC_MDIO 49 U10-5 ( 1 ) U10-10 ( 1 ) MDIO 30 Management Data I/O
HC_MDC 139 D16 U1 MDC 31 Management Data Clock
HC_RX_CLK 96 H14 J5 RX_CLK 38 MII Receive Clock
HC_RX_DV 116 E14 H5 RX_DV 39 MII Receive Data valid
HC_RX_CRS 92 H15 H4 RX_CRS 40 MII Carrier Sense
HC_RX_ERR 90 G13 H6 RX_ERR 41 MII Receive Error
HC_RX_COL 114 F14 G6 RX_COL 42 MII Collision Detect
HC_RXD[0] 102 G15 G4 RXD0 43 MII Receive Data bit 0
HC_RXD[1] 104 G12 G5 RXD1 44 MII Receive Data bit 1
HC_RXD[2] 108 F13 G7 RXD2 45 MII Receive Data bit 2
HC_RXD[3] 110 F15 F4 RXD3 46 MII Receive Data bit 3
Notes:
(1) These signals do not go through the MAX II chip. They pass through the MAX3378 level translator chip, U10.
Table 2–13. Ethernet PHY Pinout with HSMC Connector
HSMC Connector MAX II Ethernet PHY
Signal Name
Pin
No.
HSMC
Connector
Side Pin
Device
Side Pin
Signal Name
Pin
No.
Description