Altera LCD Multimedia HSMC User Manual
Page 37

2–29
Altera Corporation
LCD Multimedia HSMC
August 2008
Interfaces/ Connectors
shows the VGA/DAC interface schematic.
HC_VGA_DATA[6]
83
L16
U5
VGA_R6
45
VGA red data bus bit 6
P9
VGA_G6
7
VGA green data bus bit 6
M5
VGA_B6
20
VGA blue data bus bit 6
HC_VGA_DATA[7]
85
K16
V5
VGA_R7
46
VGA red data bus bit 7
P10
VGA_G7
8
VGA green data bus bit 7
M4
VGA_B7
21
VGA blue data bus bit 7
HC_VGA_DATA[8]
89
K18
T5
VGA_R8
47
VGA red data bus bit 8
R10
VGA_G8
9
VGA green data bus bit 8
M6
VGA_B8
22
VGA blue data bus bit 8
HC_VGA_DATA[9]
91
J18
T4
VGA_R9
48
VGA red data bus bit 9
P11
VGA_G9
10
VGA green data bus bit 9
L6
VGA_B9
23
VGA blue data bus bit 9
HC_VGA_BLANK
59
N17
R8
VGA_BLANK
11
VGA BLANK
HC_VGA_SYNC
61
N18
P7
VGA_SYNC
12
VGA SYNC
HC_VGA_CLOCK
97
J13
L4
VGA_CLOCK
24
VGA TDM Clock
Table 2–22. VGA/DAC Interface Pinout with HSMC Connector
HSMC Connector
MAX II
VGA/DAC Interface
Signal Name
Pin
No.
HSMC
Connector
Side Pin
Device
Side Pin
Signal Name
Pin
No.
Description
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)