Altera 100G Development Kit, Stratix IV GT Edition - Manual (Page 66)

2–58 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix IV GT Edition Reference Manual September 2010 Altera Corporation
U47.C10 Read data bus QDR2A_Q7 U44.AN15 —
U47.B11 Read data bus QDR2A_Q8 U44.AP16 —
U47.B2 Read data bus QDR2A_Q9 U44.AK17 —
U47.D3 Read data bus QDR2A_Q10 U44.AJ16 —
U47.E3 Read data bus QDR2A_Q11 U44.AL17 —
U47.F2 Read data bus QDR2A_Q12 U44.AK16 —
U47.G3 Read data bus QDR2A_Q13 U44.AK15 —
U47.K3 Read data bus QDR2A_Q14 U44.AM17 —
U47.L2 Read data bus QDR2A_Q15 U44.AM16 —
U47.N3 Read data bus QDR2A_Q16 U44.AL14 —
U47.P3 Read data bus QDR2A_Q17 U44.AM15 —
— Stratix IV GT RDN pin for calibrated-termination QDR2A_RDN U44.BC11 —
U47.A8 Read port select QDR2A_RPSN U44.AJ18 —
— Stratix IV GT RUP pin for calibrated-termination QDR2A_RUP U44.BC10 —
U47.A4 Write port select QDR2A_WPSN U44.AK18 —
QDR II B Interface
U48.R9 Address bus QDR2B_A0 U44.BB22 —
U48.R8 Address bus QDR2B_A1 U44.BC22 —
U48.B4 Address bus QDR2B_A2 U44.AP20 —
U48.B8 Address bus QDR2B_A3 U44.AT21 —
U48.C5 Address bus QDR2B_A4 U44.AR20 —
U48.C7 Address bus QDR2B_A5 U44.AU20 —
U48.N5 Address bus QDR2B_A6 U44.BC19 —
U48.N6 Address bus QDR2B_A7 U44.BD20 —
U48.N7 Address bus QDR2B_A8 U44.BB21 —
U48.P4 Address bus QDR2B_A9 U44.BB20 —
U48.P5 Address bus QDR2B_A10 U44.BD19 —
U48.P7 Address bus QDR2B_A11 U44.BD21 —
U48.P8 Address bus QDR2B_A12 U44.BD22 —
U48.R3 Address bus QDR2B_A13 U44.AU22 —
U48.R4 Address bus QDR2B_A14 U44.AY22 —
U48.R5 Address bus QDR2B_A15 U44.BC20 —
U48.R7 Address bus QDR2B_A16 U44.BA22 —
U48.A9 Address bus QDR2B_A17 U44.AV22 —
U48.A3 Address bus QDR2B_A18 U44.AN20 —
U48.A10 Address bus QDR2B_A19 U44.BA20 —
U48.C6 Address bus QDR2B_A20 U44.AT20 —
U48.B7 Byte write select QDR2B_BWSN0 U44.BD15 —
Table 2–39. QDR II Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 8)
Board
Reference
Description
Schematic
Signal Name
Stratix IV GT
Device
Pin Name
Other
Connections