Pll frequency setup, Pll frequency setup –28 – Altera 100G Development Kit, Stratix IV GT Edition User Manual
Page 36

2–28
Chapter 2: Board Components
Clock Circuitry
100G Development Kit, Stratix IV GT Edition Reference Manual
September 2010
Altera Corporation
PLL Frequency Setup
The PLL/buffer devices (Si5338) are pre-programmed to 706.25 MHz (U21) and
100 MHz (U22, U56). These can be dynamically programmed using the clock GUI
through their I
2
C interface.
U19.4
SMA input for differential clock buffer A
SMA_DIFF_CLKIN_P0
LVDS
—
J21.1
U19.5
SMA input for differential clock buffer A
SMA_DIFF_CLKIN_N0
—
J28.1
U19.20
Differential clock buffer A to FPGA
fabric
DIFFCLK_B5_P
AD6
—
U19.19
DIFFCLK_B5_N
AC6
—
U19.17
DIFFCLK_B6_P
W6
—
U19.16
DIFFCLK_B6_N
V6
—
U19.15
BUFFA3_SE_CLK_P
—
U14.5
U19.14
BUFFA3_SE_CLK_N
—
U14.6
U19.12
Differential buffer A to SMA
BUFFA_DIFF_CLK_P
—
J22.1
U19.11
Differential buffer A to SMA
BUFFA_DIFF_CLK_N
—
J29.1
U15.4
SMA input for reference clock buffer A
SMA_REF_CLKIN_P
—
J6.1
U15.5
SMA input for reference clock buffer A
SMA_REF_CLKIN_N
—
J12.1
U15.20
Reference clock buffer A to the
transceivers
REFCLK_QR1_P
AK43
—
U15.19
REFCLK_QR1_N
AK44
—
U15.17
REFCLK_QR2_P
V43
—
U15.16
REFCLK_QR2_N
V44
—
U15.15
BUFFA_REF_CLK_P
—
J7.1
U15.14
BUFFA_REF_CLK_N
—
J13.1
J47.1
Reference clock SMA input to FPGA
fabric
REFCLK_QR0_P
BC41
—
J54.1
REFCLK_QR0_N
BD41
—
J46.1
REFCLK_QR3_P
F43
—
J53.1
REFCLK_QR3_N
F44
—
U14.4
SMA input for single-ended clock buffer
A
SE_CLKINA_SMA
2.5-V
CMOS
—
J3.1
U14.23
Single-ended clock buffer A
SE_CLKA_L
AB6
—
U14.21
SE_CLKA_R
V39
—
U14.19
SE_CLKA_MAX
—
U72.J6
U14.13
SE_CLKOUTA_SMA
—
J4.1
U13.1
644-MHz reference clock buffer
CLK_644_P
LVDS
—
J10.1
U13.2
644-MHz reference clock buffer
CLK_644_N
—
J11.1
U67.2
50-MHz single-ended clock buffer to
FPGA fabric
CLKIN_50_FPGA
2.5-V
CMOS
AC39
—
U67.5
50-MHz single-ended clock to MAX
CLKIN_50_MAX
—
U72.J13
Table 2–14. Spread Spectrum Configuration DIP Switch Pin-Out (SW2) (Part 3 of 3)
Board
Reference
Description
Schematic
Signal Name
I/O
Standard
Stratix IV
GT Device
Pin Name
Other
Connections