Altera 100G Development Kit, Stratix IV GT Edition - Manual (Page 58)

2–50 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix IV GT Edition Reference Manual September 2010 Altera Corporation
U37.D7 Data bus DDR3A_DQ8 U44.E11 —
U37.C3 Data bus DDR3A_DQ9 U44.D11 —
U37.C8 Data bus DDR3A_DQ10 U44.F11 —
U37.C2 Data bus DDR3A_DQ11 U44.E13 —
U37.A7 Data bus DDR3A_DQ12 U44.F13 —
U37.A2 Data bus DDR3A_DQ13 U44.D12 —
U37.B8 Data bus DDR3A_DQ14 U44.F12 —
U37.A3 Data bus DDR3A_DQ15 U44.D10 —
U36.E3 Data bus DDR3A_DQ16 U44.K13 —
U36.F7 Data bus DDR3A_DQ17 U44.J14 —
U36.F2 Data bus DDR3A_DQ18 U44.J12 —
U36.F8 Data bus DDR3A_DQ19 U44.L14 —
U36.H3 Data bus DDR3A_DQ20 U44.G12 —
U36.H8 Data bus DDR3A_DQ21 U44.H13 —
U36.G2 Data bus DDR3A_DQ22 U44.J13 —
U36.H7 Data bus DDR3A_DQ23 U44.H14 —
U36.D7 Data bus DDR3A_DQ24 U44.N17 —
U36.C3 Data bus DDR3A_DQ25 U44.N15 —
U36.C8 Data bus DDR3A_DQ26 U44.R15 —
U36.C2 Data bus DDR3A_DQ27 U44.N16 —
U36.A7 Data bus DDR3A_DQ28 U44.P14 —
U36.A2 Data bus DDR3A_DQ29 U44.M14 —
U36.B8 Data bus DDR3A_DQ30 U44.P17 —
U36.A3 Data bus DDR3A_DQ31 U44.N14 —
U37.G3 Data strobe N byte lane 0 DDR3A_DQS_N0 U44.A13 —
U37.F3 Data strobe P byte lane 0 DDR3A_DQS_P0 U44.B13 —
U37.B7 Data strobe N byte lane 1 DDR3A_DQS_N1 U44.E14 —
U37.C7 Data strobe P byte lane 1 DDR3A_DQS_P1 U44.F14 —
U36.G3 Data strobe N byte lane 2 DDR3A_DQS_N2 U44.J15 —
U36.F3 Data strobe P byte lane 2 DDR3A_DQS_P2 U44.K15 —
U36.B7 Data strobe N byte lane 3 DDR3A_DQS_N3 U44.P16 —
U36.C7 Data strobe P byte lane 3 DDR3A_DQS_P3 U44.R16 —
U36.K1, U37.K1 On-die termination DDR3A_ODT U44.G15 —
U36.J3, U37.J3 Row address select DDR3A_RASN U44.H23 —
U36.T2, U37.T2 Reset DDR3A_RSTN U44.G23 —
U36.L3, U37.L3 Write enable DDR3A_WEN U44.G25 —
DDR3B Interface
U39.N3, U38.N3 Address bus DDR3B_A0 U44.G21 —
Table 2–37. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 8)
Board Reference Description
Schematic
Signal Name
Stratix IV GT
Device
Pin Name
Other
Connections