Altera 100G Development Kit, Stratix IV GT Edition - Manual (Page 11)

Chapter 2: Board Components 2–3
Board Overview
September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual
D12-D17
Ethernet status LEDs Shows the Ethernet connection speed as well as transmit or receive
activity.
D26 Factory LED Illuminates when the factory design is being loaded into the FPGA.
D36 Load LED Illuminates when the FPGA is being loaded.
D38 Error LED Illuminates when the FPGA configuration from flash fails.
D40 Configuration done LED Illuminates when the FPGA is configured.
J40 USB_DISABLE
Manually disables the embedded USB-Blaster when you install the
jumper. Otherwise, the embedded USB-Blaster is enabled.
J41 JTAG_EN
Enables the MAX II CPLD EPM2210 System Controller to be in the JTAG
chain when shunted
J61 JTAG programming header
JTAG programming header for connecting an Altera USB-Blaster dongle
to program the FPGA and MAX II CPLD devices.
J58
JTAG for embedded
USB-Blaster MAX II CPLD
JTAG for embedded USB-Blaster MAX II CPLD device programming.
S9 CPU reset push-button Press to reset the FPGA logic.
S10 PGM_SEL push-button Selects design file to load into the FPGA.
S11 Load push-button Initiates loading of the FPGA.
S12 Factory push-button Initiates loading of factory design into the FPGA.
SW2
Board settings DIP switch Controls the MAX II CPLD EPM2210 System Controller functions such as
clock enable, power and temperature monitor, as well as voltage settings
for transceivers and SMA clock input control.
U72 MAX II CPLD (System)
Altera EPM2210F324C3N, MAX II 256-pin CPLD for MAX II+FPP
configuration.
U80
MAX II CPLD (Embedded
USB-Blaster) Altera EPM240M100C4N, MAX II CPLD for embedded USB-Blaster
circuitry.
Clock Circuitry
J6, J12
J21, J28
J18, J25
J19, J26
J3, J14
SMA input clocks
Reference clock for Interlaken side LVDS.
Differential clock for Interlaken side LVDS.
Reference clock for line side LVDS.
Differential clock for line side LVDS.
Single-ended clock inputs.
J10, J11
J7, J13
J22, J29
J17, J24
J27, J20
J4, J15
J8, J9
J45, J52
SMA output clocks
644.53125-MHz LVDS clock.
Reference clock SMA output for Interlaken side LVDS.
Differential clock SMA output for Interlaken side LVDS.
Reference clock SMA output for line side LVDS.
Differential clock SMA output for line side LVDS.
Single-ended clock SMA outputs.
Optical clock SMA source.
PLL output of FPGA.
J47, J54,
J46, J53
SMA input clock for XCVR
reference clock
XCVR reference clock for external clock source (LVPECL or LVDS).
Table 2–1. Stratix IV GT 100G Development Board Components (Part 2 of 5)
Board
Reference
Type Description